\doxysubsubsubsection{DMA interrupt enable definitions }
\hypertarget{group___d_m_a__interrupt__enable__definitions}{}\label{group___d_m_a__interrupt__enable__definitions}\index{DMA interrupt enable definitions@{DMA interrupt enable definitions}}


DMA interrupts definition.  


\doxysubsubsubsubsubsection*{Macros}
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\#define {\bfseries DMA\+\_\+\+IT\+\_\+\+TC}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6ae47cc2cd2e985d29cb6b0bb65da1d7}{DMA\+\_\+\+Sx\+CR\+\_\+\+TCIE}})
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\Hypertarget{group___d_m_a__interrupt__enable__definitions_gadf11c572b9797e04a14b105fdc2e5f66}\label{group___d_m_a__interrupt__enable__definitions_gadf11c572b9797e04a14b105fdc2e5f66} 
\#define {\bfseries DMA\+\_\+\+IT\+\_\+\+HT}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga13a7fe097608bc5031d42ba69effed20}{DMA\+\_\+\+Sx\+CR\+\_\+\+HTIE}})
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\Hypertarget{group___d_m_a__interrupt__enable__definitions_gaf9d92649d2a0146f663ff253d8f3b59e}\label{group___d_m_a__interrupt__enable__definitions_gaf9d92649d2a0146f663ff253d8f3b59e} 
\#define {\bfseries DMA\+\_\+\+IT\+\_\+\+TE}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaeee99c36ba3ea56cdb4f73a0b01fb602}{DMA\+\_\+\+Sx\+CR\+\_\+\+TEIE}})
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\Hypertarget{group___d_m_a__interrupt__enable__definitions_ga71137443f7bdced1ee80697596e9ea98}\label{group___d_m_a__interrupt__enable__definitions_ga71137443f7bdced1ee80697596e9ea98} 
\#define {\bfseries DMA\+\_\+\+IT\+\_\+\+DME}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gacaecc56f94a9af756d077cf7df1b6c41}{DMA\+\_\+\+Sx\+CR\+\_\+\+DMEIE}})
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\Hypertarget{group___d_m_a__interrupt__enable__definitions_ga93164ec039fc5579662c382e68d7d13f}\label{group___d_m_a__interrupt__enable__definitions_ga93164ec039fc5579662c382e68d7d13f} 
\#define {\bfseries DMA\+\_\+\+IT\+\_\+\+FE}~((uint32\+\_\+t)0x00000080U)
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\doxysubsubsubsubsection{Detailed Description}
DMA interrupts definition. 

